35 Important MCQ On Microprocessors And Microcontrollers

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1. The fetch and execute instruction, one at a time, in the order of address increment is identified as

  1. The Instruction execution technique
  2. The Straight line sequencing technique
  3. The Instruction fetching technique
  4. The Random sequencing technique

Answer – (2)

2. The control signal employed to differentiate amongst an input  or output operation and memory operations is

  1. ALE
  2. IO/ M͞
  3. SID
  4. SOD

Answer – (2)

3. The instruction register hold

  1. The Flag condition
  2. An Instruction address
  3. An Opcode
  4. None

Answer – (3)

4. A microprocessor is termed to be a 8-bit or 16-bit or more considering the

  1. Size of data bus
  2. Size of Address bus
  3. Size of Arithmetic Logic Unit
  4. Size of Control bus

Answer – (3)

5. The number of pair register  found in 8085 microprocessor

  1. Three
  2. Four
  3. two
  4. Zero

Answer – (1)

6. The number of programmable 8-bit registers of microprocessor 8085 is

  1. five
  2. Six
  3. Seven
  4. Eight

Answer – (3)

7. The stack and SP in microprocessor

  1. Belong to the memory
  2. Both reside in CPU
  3. Both reside in memory and later in CPU
  4. Former reside in CPU and the later in memory

Answer – (3)

8. An 8kX8 ROM, having the monitor program of microprocessor trainer-kit with end-address of

  1. 600FH
  2. 500FH
  3. 1 FFF H
  4. 4 FFF H

Answer – (3)

9. The overall I/O space existing in a 8085 if used as a peripheral mapped mode

  1. Sixty four only
  2. One hundred twenty eight
  3. Two hundred fifty six
  4. Five hundred twelve

Answer – (3)

10. The interfacing device utilized with an O/P port be there

  1. Buffer circuit
  2. Priority encoder circuit
  3. Latch circuit
  4. None

Answer – (1)

11. Address lines necessitate for the 64kB memory is

  1. 24
  2. 36
  3. 12
  4. 16

Answer – (4)

12. Which one is hardware type interrupt?

  1. INTA
  2. TRAP
  3. RST
  4. INT

Answer – (2)

13. In 8085 microprocessor, which one is the non-maskable interrupt?

  1. RST 7.5
  2. TRAP
  3. HOLD
  4. INTR

Answer – (2)

14. Machine cycles in the “CALL” instruction of microprocessor 8085 CPU are

  1. six
  2. five
  3. four
  4. two

Answer – (2)

15. In 8085 Microprocessor, the interrupt TRAP is

  1. Every time maskable
  2. not interrupted  by a service subroutine
  3. Used for short-term power failure
  4. Lowermost priority interrupt

Answer – (3)

16. RST 7.5 interrupt act as

  1. Vectored and Maskable type
  2. Vectored and non-maskable type
  3. Direct and maskable type
  4. Direct and non-maskable type

Answer – (1)

17. No of hardware interrupt request, a solitary interrupt- controller  namely IC8259A could process?

  1. Eight
  2. Nine
  3. Sixteen
  4. Sixty four

Answer – (1)

18. The interrupt mask in the 8085 microprocessor is set or reset by the software instruction

  1. By the EI interrupt
  2. By the DI interrupt
  3. By the RIM interrupt
  4. By the SIM interrupt

Answer – (4)

19. For 8085, The vector address corresponding to software interrupt RST 7.0 is

  1. 0017 Hex
  2. 0027 Hex
  3. 0038 Hex
  4. 0700 Hex

Answer – (3)

20. Which one has the highest priority out of these

  1. TRAP
  2. RST 7.5
  3. RST 6.5
  4. HOLD

Answer – (4)

21. Which one of the following is the software interrupt of 8085 ?

  1. RST 7.5
  2. EI
  3. RST 1.0
  4. TRAP

Answer – (3)

22. Let the accumulator content 4F after execution the RAL instruction, contain of accumulator will be

  1. 9E
  2. 8B
  3. 8C

Answer – (1)

23. The clock’s interrupt-handler of a certain computational machine needs 2 m/sec per clock tick. The clock’s frequency is 60 Hz. What percent of the CPU is dedicated to the clk?

  1. 1.2
  2. 7.5
  3. 12
  4. 18.5

Answer – (3)

24. For “JZ NEXT” instruction, which of the following register’s memory is checked to verify if it is ‘0’ or not ?

  1. A
  2. B
  3. R1
  4. R2

Answer – (1)

25. At any time POP H instruction is performed

  1. Data bytes in the HL pairs will be put in storage of the stack’s registers
  2. Two data bytes are transferred to the HL pair’s register
  3. Two data bytes at the top of the stack are moved to the CPU

Answer – (2)

26. In microprocessor instruction STA 9000H is  

  1. A data transfer instruction
  2. A Logical instruction
  3. A I/O and MPU will execute
  4. Not an option

Answer – (1)

27. The addressing method in microprocessor used in the STAX B is

  1. A Direct addressing method
  2. A Resister addressing  method
  3. An Immediate addressing method
  4. Register indirect addressing method

Answer – (4)

28. When a subroutine is called the address of the instruction next to CALL is kept in

  1. The Stack
  2. The Program counter
  3. The Stack pointer register
  4. Not an option

Answer – (1)

29. Machine cycles for IN instructions in microprocessor are

  1. Eight
  2. five
  3. four
  4. three

Answer – (4)

 30. The instruction MOV A, B is kind of

  1. the Immediate addressing mode
  2. Directing addressing mode
  3. Implied addressing mode
  4. Register addressing mode

Answer – (4)

31. How many T-states would be required for the execution of CALL 2000 H instruction?

  1. 10
  2. 13
  3. 18
  4. None of these

Answer – (3)

32. The number of I/O lines for 8255 chip is

  1. 256
  2. 512
  3. 1024
  4. 2K

Answer – (1)

33. How many flag registers are available in the 8051 chip?

  1. 9
  2. 8
  3. 6
  4. 5
  5. None

Answer – (5)

34. The “programmable interval timer” is

  1. 8253 chip
  2. 8251 chip
  3. 8250 chip
  4. 8275 chip

Answer – (1)

35. The 8086 microprocessor addressing capacity is

  1. 64 KB
  2. 1 MB
  3. 2 MB
  4. 1 GB

Answer – (2)

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